RXUIS=Val_0x0, RXOIS=Val_0x0, RXFIS=Val_0x0, MSTIS=Val_0x0, TXOIS=Val_0x0, TXEIS=Val_0x0
Interrupt Status Register
| TXEIS | Transmit FIFO Empty Interrupt Status. 0 (Val_0x0): Transmit FIFO Empty interrupt is not active after masking 1 (Val_0x1): Transmit FIFO Empty interrupt is active after masking |
| TXOIS | Transmit FIFO Overflow Interrupt Status. 0 (Val_0x0): Transmit FIFO Overflow interrupt is not active after masking 1 (Val_0x1): Transmit FIFO Overflow interrupt is active after masking |
| RXUIS | Receive FIFO Underflow Interrupt Status. 0 (Val_0x0): Receive FIFO Underflow interrupt is not active after masking 1 (Val_0x1): Receive FIFO Underflow interrupt is active after masking |
| RXOIS | Receive FIFO Overflow Interrupt Status. 0 (Val_0x0): Receive FIFO Overflow interrupt is not active after masking 1 (Val_0x1): Receive FIFO Overflow interrupt is active after masking |
| RXFIS | Receive FIFO Full Interrupt Status. 0 (Val_0x0): Receive FIFO Full interrupt is not active after masking 1 (Val_0x1): Receive FIFO Full interrupt is active after masking |
| MSTIS | Multi-Master Contention Interrupt Status. This bit is not present if the SPI is configured as a serial slave device. 0 (Val_0x0): Multi-Master Contention interrupt is not active after masking 1 (Val_0x1): Multi-Master Contention interrupt is active after masking |